Quick Detail:
High Performance E2CMOS PLD Generic Array Logicâ„¢
Description:
The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures listed in the table of the macrocell description section. GAL20V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Applications:
• HIGH PERFORMANCE E2
CMOS® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL®
Devices with Full Function/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
Specifications:
Datasheets | GAL20V8 |
PCN Obsolescence | Multiple Devices 07/Sept/2010 |
Standard Package | 15 |
Category | Integrated Circuits (ICs) |
Family | Embedded - CPLDs (Complex Programmable Logic Devices) |
Series | GAL®20V8 |
Packaging | Tube |
Programmable Type | EE PLD |
Delay Time tpd(1) Max | 15.0ns |
Voltage Supply - Internal | 4.75 V ~ 5.25 V |
Number of Logic Elements/Blocks | - |
Number of Macrocells | 8 |
Number of Gates | - |
Number of I /O | - |
Operating Temperature | 0°C ~ 75°C |
Mounting Type | Through Hole |
Package / Case | 24-DIP (0.300", 7.62mm) |
Supplier Device Package | 24-PDIP |
Competitive Advantage:
Warranty :180 days !
Free shipping: Order over $1000 win a free shipment fee
(goods weight below 3Kg) ,during 20130901-20130930 .
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GAL20V8B-15QPN - Lattice Semiconductor - High Performance E2CMOS PLD Generic Array Logic™ Images
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